Continuing advances in semiconductor fabrication technology have lead to VLSI (very large scale integration) integrated circuit designs with greater numbers of faster components connected by increasing numbers of longer interconnects. These interconnects may be the source of design concerns like signal quality associated with induced signals, timing delays, and so on. As interconnects get longer and circuits become more complicated, clock skew may also grow as a design issue.
Timing delays and clock skew may be issues because circuits are clocked to facilitate keeping signals correlated in time. For example, for a flip flop to correctly capture data, the data provided to the flip flop must be stable for a period of time Tsetup before a relevant clock edge arrives. Similarly, for a flip flop to correctly latch data, the data provided to the flip flop must be stable for a period of time Thold after a relevant clock edge arrives. If a clocked network of circuit components has an unbalanced clock delay, then the relevant clock edge may arrive at different times at different circuit components leading to undesired and/or unanticipated results. Thus, the combination of clock skew, Tsetup, and Thold requirements may complicate connecting circuit components via interconnects. While a flip flop is described as an example circuit component it is to be appreciated that timing delays and clock skew may affect other circuit components (e.g., clocked logics like latches) referred to more generally as receivers.
In one example, a microprocessor environment, interconnect lengths between and within microprocessor datapath blocks may produce performance bottlenecks. For example, interconnect capacitance per unit length, which may be dominated by sidewall fringing and coupling, may induce clock skews and delay variations. Setup time and hold time timing requirements for distributed receivers connected to such long, high-speed, on-chip interconnects may be more difficult to achieve due, for example, to shrinking cycle times and overlapping noise sources.